L4Re Operating System Framework
Interface and Usage Documentation
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uart_16550.h
1/* SPDX-License-Identifier: GPL-2.0-only OR License-Ref-kk-custom */
2/*
3 * Copyright (C) 2023 Kernkonzept GmbH.
4 */
5/*
6 * (c) 2008-2012 Adam Lackorzynski <adam@os.inf.tu-dresden.de>
7 * Alexander Warg <alexander.warg@os.inf.tu-dresden.de>
8 * economic rights: Technische Universität Dresden (Germany)
9 *
10 * This file is part of TUD:OS and distributed under the terms of the
11 * GNU General Public License 2.
12 * Please see the COPYING-GPL-2 file for details.
13 */
14#pragma once
15
16#include "uart_base.h"
17
18namespace L4
19{
20 class Uart_16550 : public Uart
21 {
22 protected:
23 enum Registers
24 {
25 TRB = 0x00, // Transmit/Receive Buffer (read/write)
26 BRD_LOW = 0x00, // Baud Rate Divisor LSB if bit 7 of LCR is set (read/write)
27 IER = 0x01, // Interrupt Enable Register (read/write)
28 BRD_HIGH = 0x01, // Baud Rate Divisor MSB if bit 7 of LCR is set (read/write)
29 IIR = 0x02, // Interrupt Identification Register (read only)
30 FCR = 0x02, // 16550 FIFO Control Register (write only)
31 LCR = 0x03, // Line Control Register (read/write)
32 MCR = 0x04, // Modem Control Register (read/write)
33 LSR = 0x05, // Line Status Register (read only)
34 MSR = 0x06, // Modem Status Register (read only)
35 SPR = 0x07, // Scratch Pad Register (read/write)
36 };
37
38 enum Register_value_iir
39 {
40 IIR_BUSY = 7,
41 };
42
43 enum Register_value_lsr
44 {
45 LSR_DR = 0x01, // Receiver data ready
46 LSR_THRE = 0x20, // Transmit hold register empty
47 LSR_TSRE = 0x40, // Transmitter empty
48 };
49
50 public:
51 enum
52 {
53 PAR_NONE = 0x00,
54 PAR_EVEN = 0x18,
55 PAR_ODD = 0x08,
56 DAT_5 = 0x00,
57 DAT_6 = 0x01,
58 DAT_7 = 0x02,
59 DAT_8 = 0x03,
60 STOP_1 = 0x00,
61 STOP_2 = 0x04,
62
63 MODE_8N1 = PAR_NONE | DAT_8 | STOP_1,
64 MODE_7E1 = PAR_EVEN | DAT_7 | STOP_1,
65
66 // these two values are to leave either mode
67 // or baud rate unchanged on a call to change_mode
68 MODE_NC = 0x1000000,
69 BAUD_NC = 0x1000000,
70
71 Base_rate_x86 = 115200,
72 Base_rate_pxa = 921600,
73 };
74
75 explicit Uart_16550(unsigned long base_rate, unsigned char init_flags = 0,
76 unsigned char ier_bits = 0,
77 unsigned char mcr_bits = 0, unsigned char fcr_bits = 0)
78 : _base_rate(base_rate), _init_flags(init_flags), _mcr_bits(mcr_bits),
79 _ier_bits(ier_bits), _fcr_bits(fcr_bits)
80 {}
81
82 bool startup(Io_register_block const *regs) override;
83 void shutdown() override;
84 bool change_mode(Transfer_mode m, Baud_rate r) override;
85 int get_char(bool blocking = true) const override;
86 int char_avail() const override;
87 int tx_avail() const;
88 void wait_tx_done() const;
89 inline void out_char(char c) const;
90 int write(char const *s, unsigned long count,
91 bool blocking = true) const override;
92 bool enable_rx_irq(bool enable = true) override;
93
94 private:
95 unsigned long _base_rate;
96 unsigned char _init_flags;
97 unsigned char _mcr_bits;
98 unsigned char _ier_bits;
99 unsigned char _fcr_bits;
100 };
101}
L4 low-level kernel interface.
Definition io_regblock.h:19