# ARCH:           ARM arm
# ARCHDESCR:      ARM processor family
#
# ARCHSELECT:     BIT32 if !BIT64
# ARCHSELECT:     HAS_FPU_OPTION
# ARCHSELECT:     HAS_COV_OPTION
# ARCHSELECT:     FPU if CPU_VIRT
# ARCHSELECT:     ARM_LPAE if MMU && (CPU_VIRT || BIT64)
# ARCHSELECT:     HAS_SERIAL_OPTION
# ARCHSELECT:     HAS_JDB_DISASM_OPTION
# ARCHSELECT:     HAS_JDB_GZIP_OPTION
# ARCHSELECT:     HAS_VIRT_OBJ_SPACE_OPTION if ARM_V6PLUS && !CPU_VIRT && !ARM_1176_CACHE_ALIAS_FIX
# ARCHSELECT:     HAS_LAZY_FPU
# ARCHSELECT:     HAS_SYNC_CLOCK if USE_GENERIC_TIMER
# ARCHSELECT:     HAS_ONE_SHOT if SYNC_CLOCK
# ARCHSELECT:     HAS_TICKLESS_IDLE
# ARCHSELECT:     HAS_IRQ_DIRECT_INJECT_OPTION
#
# ARCHDEFAULTPF: PF_ARM_VIRT

# SECTION: GLOBAL

config HAS_64BIT
	bool

config CAN_ARM_CPU_SA1100
	bool

config CAN_ARM_CPU_XSCALE
	bool

config CAN_ARM_CPU_920T
	bool

config CAN_ARM_CPU_926
	bool

config CAN_ARM_CPU_1136
	bool

config CAN_ARM_CPU_1176
	bool

config CAN_ARM_CPU_MPCORE
	bool

config CAN_ARM_CPU_CORTEX_A5
	bool

config CAN_ARM_CPU_CORTEX_A7
	bool

config CAN_ARM_CPU_CORTEX_A8
	bool

config CAN_ARM_CPU_CORTEX_A9
	bool

config CAN_ARM_CPU_CORTEX_A15
	bool

config CAN_ARM_CPU_KRAIT
	bool

config CAN_ARM_CACHE_L2CXX0
	bool

config CAN_ARM_CPU_CORTEX_A35
	bool

config CAN_ARM_CPU_CORTEX_A53
	bool

config CAN_ARM_CPU_CORTEX_A55
	bool

config CAN_ARM_CPU_CORTEX_A57
	bool

config CAN_ARM_CPU_CORTEX_A72
	bool

config CAN_ARM_CPU_CORTEX_A76
	bool

config CAN_ARM_CPU_NEOVERSE_N1
	bool

config CAN_ARM_CPU_V8R
	bool

config CAN_ARM_CPU_CORTEX_R52
	bool

config CAN_ARM_CPU_CORTEX_R82
	bool

config DEFAULT_ARM_EM_TZ
	bool

config DEFAULT_ARM_EM_NS
	bool

config DONT_USE_GENERIC_TIMER
	bool

config USE_GENERIC_TIMER
	def_bool y if HAS_CPU_VIRT
	depends on !DONT_USE_GENERIC_TIMER

config ARM_V6
	def_bool y if ARM_1136 || ARM_1176 || ARM_MPCORE

config ARM_V7
	def_bool y if ARM_CORTEX_A8 || ARM_CORTEX_A9 \
	              || ARM_CORTEX_A5 || ARM_CORTEX_A7 || ARM_CORTEX_A15

config ARM_V6PLUS
	def_bool y if ARM_V6 || ARM_V7 || ARM_V8

config ARM_V7PLUS
	def_bool y if ARM_V7 || ARM_V8

config ARM_V8PLUS
	def_bool y if ARM_V8

config ARM_V8
	bool

config ARM_ACPI
	bool

config ARM_GIC
	bool

config HAVE_ARM_GICV2
	bool

config HAVE_ARM_GICV3
	bool

config HAVE_ARM_GIC_MSI
	bool

config ARM_GIC_NOT_COHERENT
	bool

config ARM_IOMMU_COHERENT
	bool

config HAS_IOMMU_ARM_SMMU_400
	bool
	select HAS_IOMMU_OPTION

config HAS_IOMMU_ARM_SMMU_500
	bool
	select HAS_IOMMU_OPTION

config HAS_IOMMU_ARM_SMMU_V3
	bool
	select HAS_IOMMU_ARM_SMMU_V3_ON_64BIT if BIT64

# SMMUv3 implementation in Fiasco currently only supports the AArch64 page
# table format, which is not defined on Aarch32, so limit the IOMMU option
# to 64-bit.
config HAS_IOMMU_ARM_SMMU_V3_ON_64BIT
	bool
	select HAS_IOMMU_OPTION

config IOMMU_ARM_SMMU_400
	def_bool y if IOMMU
	depends on HAS_IOMMU_ARM_SMMU_400

config IOMMU_ARM_SMMU_500
	def_bool y if IOMMU
	depends on HAS_IOMMU_ARM_SMMU_500

config IOMMU_ARM_SMMU_V3
	def_bool y if IOMMU
	depends on HAS_IOMMU_ARM_SMMU_V3_ON_64BIT

config ARM_ASID16
	depends on ARM_V8 && BIT64
	bool

config HAS_ARM_SVE
	bool

config ARM_PROFILE_A
	bool
	default y if !ARM_PROFILE_R

config ARM_PROFILE_R
	select SYNC_CLOCK
	bool

# SECTION: CPU

choice
	prompt "CPU"
	default ARM_926    if ARM

config ARM_PXA
	bool "Intel XScale"
	depends on PF_XSCALE

config ARM_SA
	bool "Intel StrongARM"
	depends on PF_SA1100

config ARM_920T
	bool "ARM 920T Processor"
	depends on PF_S3C2410

config ARM_926
	bool "ARM 926 Processor"
	depends on CAN_ARM_CPU_926

config ARM_1136
	bool "ARM 1136 CPU"
	depends on CAN_ARM_CPU_1136

config ARM_1176
	bool "ARM 1176 CPU"
	depends on CAN_ARM_CPU_1176

config ARM_MPCORE
	bool "ARM MPCore CPU"
	depends on CAN_ARM_CPU_MPCORE
	select HAS_MP_OPTION

config ARM_CORTEX_A5
	bool "ARM Cortex-A5 CPU"
	depends on CAN_ARM_CPU_CORTEX_A5

config ARM_CORTEX_A7
	bool "ARM Cortex-A7 CPU"
	depends on CAN_ARM_CPU_CORTEX_A7
	select HAS_MP_OPTION
	select HAS_CPU_VIRT if ARM_GIC

config ARM_CORTEX_A8
	bool "ARM Cortex-A8 CPU"
	depends on CAN_ARM_CPU_CORTEX_A8

config ARM_CORTEX_A9
	bool "ARM Cortex-A9 CPU"
	depends on CAN_ARM_CPU_CORTEX_A9
	select HAS_MP_OPTION

config ARM_CORTEX_A15
	bool "ARM Cortex-A15 CPU"
	depends on CAN_ARM_CPU_CORTEX_A15
	select HAS_MP_OPTION
	select HAS_CPU_VIRT if ARM_GIC

config ARM_CORTEX_A35
	bool "ARM Cortex-A35 CPU"
	depends on CAN_ARM_CPU_CORTEX_A35
	select ARM_V8
	select HAS_MP_OPTION
	select HAS_CPU_VIRT if ARM_GIC
	select HAS_64BIT

config ARM_CORTEX_A53
	bool "ARM Cortex-A53 CPU"
	depends on CAN_ARM_CPU_CORTEX_A53
	select ARM_V8
	select HAS_MP_OPTION
	select HAS_CPU_VIRT if ARM_GIC
	select HAS_64BIT

config ARM_CORTEX_A55
	bool "ARM Cortex-A55 CPU"
	depends on CAN_ARM_CPU_CORTEX_A55
	select ARM_V8
	select HAS_MP_OPTION
	select HAS_CPU_VIRT if ARM_GIC
	select HAS_64BIT

config ARM_CORTEX_A57
	bool "ARM Cortex-A57 CPU"
	depends on CAN_ARM_CPU_CORTEX_A57
	select ARM_V8
	select HAS_MP_OPTION
	select HAS_CPU_VIRT if ARM_GIC
	select HAS_64BIT

config ARM_CORTEX_A72
	bool "ARM Cortex-A72 CPU"
	depends on CAN_ARM_CPU_CORTEX_A72
	select ARM_V8
	select HAS_MP_OPTION
	select HAS_CPU_VIRT if ARM_GIC
	select HAS_64BIT

config ARM_CORTEX_A76
	bool "ARM Cortex-A76 CPU"
	depends on CAN_ARM_CPU_CORTEX_A76
	select ARM_V8
	select HAS_MP_OPTION
	select HAS_CPU_VIRT if ARM_GIC
	select HAS_64BIT

config ARM_NEOVERSE_N1
	bool "ARM Neoverse-N1 CPU"
	depends on CAN_ARM_CPU_NEOVERSE_N1
	select ARM_V8
	select HAS_MP_OPTION
	select HAS_CPU_VIRT if ARM_GIC
	select HAS_64BIT

config ARM_KRAIT
	bool "Qualcomm Krait"
	depends on CAN_ARM_CPU_KRAIT
	select ARM_V7
	select HAS_MP_OPTION

config ARM_V8R_GENERIC
	bool "Generic Armv8-R CPU"
	depends on CAN_ARM_CPU_V8R
	select ARM_V8
	select ARM_PROFILE_R
	select HAS_CPU_MPU
	select HAS_CPU_VIRT
	select HAS_CPU_AMP_OPTION if BIT32
	select HAS_MP_OPTION if BIT64
	select HAS_64BIT

config ARM_CORTEX_R52
	bool "ARM Cortex-R52 CPU"
	depends on CAN_ARM_CPU_CORTEX_R52
	select ARM_V8
	select ARM_PROFILE_R
	select HAS_CPU_MPU
	select HAS_CPU_VIRT
	select HAS_CPU_AMP_OPTION

config ARM_CORTEX_R82
	bool "ARM Cortex-R82 CPU"
	depends on CAN_ARM_CPU_CORTEX_R82
	select ARM_V8
	select ARM_PROFILE_R
	select BIT64_CHOICE
	select HAS_CPU_MPU
	select HAS_CPU_VIRT
	select HAS_MP_OPTION
	select HAS_64BIT

endchoice

# SECTION: TARGET

config HAVE_ARM_SECMONIF_NONE
	bool

config HAVE_ARM_SECMONIF_MC
	bool

config ARM_GIC_MSI
	bool "Enable MSI support (GIC LPIs)"
	default y
	depends on HAVE_ARM_GIC_MSI
	help
	  Build Fiasco with support for message-based interrupts (MSIs).

config ARM_SVE
	bool "Scalable Vector Extension support"
	depends on ARM_V8 && FPU && BIT64
	depends on HAS_ARM_SVE
	help
	  The ARM Scalable Vector Extension (SVE) extends the SIMD functionality
	  of the AArch64 execution state with support for larger and flexible
	  vector lengths.

	  This option also enables the SVE2 extension on CPUs that support it.

	  Enabling this option adds a small amount of overhead to FPU context
	  switching, even for contexts that do not make use of SVE.

config ARM_ALIGNMENT_CHECK
	bool "Enable alignment check"
	help
	  Enable if you want to have alignment check enabled.

choice
	prompt "Execution Model"
	default ARM_EM_NS  if DEFAULT_ARM_EM_NS
	default ARM_EM_TZ  if DEFAULT_ARM_EM_TZ
	default ARM_EM_STD if !DEFAULT_ARM_EM_NS && !DEFAULT_ARM_EM_TZ

config ARM_EM_STD
	bool "Standard mode"
	help
	  Systems without ARM TrustZone support, or no specific TrustZone
	  support.

config ARM_EM_NS
	bool "TrustZone normal side"
	depends on ARM_1176 || ARM_CORTEX_A7 || ARM_CORTEX_A8 || ARM_CORTEX_A9 \
		   || ARM_CORTEX_A15 || ARM_CORTEX_A35 || ARM_CORTEX_A53 \
		   || ARM_CORTEX_A57 || ARM_CORTEX_A72
	help
	  In a system with ARM TrustZone extension, run on the normal side.

config ARM_EM_TZ
	bool "TrustZone secure side"
	depends on !CPU_VIRT && BIT32
	depends on ARM_1176 || ARM_CORTEX_A7 || ARM_CORTEX_A8 || ARM_CORTEX_A9 \
		   || ARM_CORTEX_A15 || ARM_CORTEX_A35 || ARM_CORTEX_A53 \
		   || ARM_CORTEX_A57 || ARM_CORTEX_A72
	help
	  In a system with ARM TrustZone extension, run on the secure side,
	  and allow monitor services.

endchoice

choice
	prompt "Secure Monitor Interface"
	depends on ARM_EM_NS

config ARM_SECMONIF_NONE
	bool "None"
	depends on HAVE_ARM_SECMONIF_NONE
	help
	  Running on a minimal secure monitor that does not require
	  any interaction (e.g., u-boot for KVM).

config ARM_SECMONIF_MC
	bool "Mobicore"
	depends on HAVE_ARM_SECMONIF_MC

endchoice

menuconfig ARM_SMC_USER
	bool "Enable SMC user interface"
	depends on !ARM_EM_TZ && ARM_V6PLUS && !ARM_1136
	depends on !ARM_PROFILE_R
	help
	  When enabled then Fiasco offers an interface that allows user threads
	  to talk to SMC services. The allowed services call ranges can be
	  configured. All other SMC calls will be blocked.

if ARM_SMC_USER

config ARM_SMC_USER_MIN
	hex "Minimum SMC service call range (inclusive)"
	default 0x30000000

config ARM_SMC_USER_MAX
	hex "Maximum SMC service call range (inclusive)"
	default 0x3F000000

endif # ARM_SMC_USER

config BIT64_CHOICE
	bool "Run Fiasco in 64bit processor mode"
	default y
	depends on HAS_64BIT
	select BIT64

config ARM_CACHE_L2CXX0
	bool "Enable L2 Cache"
	default y
	depends on CAN_ARM_CACHE_L2CXX0
	help
	  Enable L2 cache functionality.

config ARM_ENABLE_SWP
	bool "Enable the deprecated 'swp' instruction"
	depends on ARM_CORTEX_A9 || ARM_CORTEX_A15 || ARM_CORTEX_A7 || ARM_CORTEX_A5
	help
	  Enabling this option enables the deprecated 'swp' instruction.
	  Avoid to enable it.

config ARM_LPAE
	bool "Use LPAE page table format"
	depends on ARM_CORTEX_A15 || ARM_CORTEX_A7 || ARM_V8
	depends on MMU
	help
	  Use the extended page table format (LPAE).

config ARM_PT48
	bool "Support user-level address space of 48bits (256 TiB)"
	depends on CPU_VIRT && BIT64 && MMU
	help
	  Build Fiasco with 4-level page-tables for user-level tasks. Requires
	  a CPU model that supports at least 44bit physical addresses.

config HAS_ARM_PSCI
	bool

config HAS_ARM_PSCI_DYNAMIC
	bool

config FORCE_ARM_PSCI_SMC
	bool

config FORCE_ARM_PSCI_HVC
	bool

config ARM_PSCI
	bool "Use PSCI"
	depends on HAS_ARM_PSCI
	help
	  Use the "Power State Coordination Interface" (PSCI) for system
	  functions such as booting CPUs and system reset.

choice
	prompt "PSCI call method"
	depends on ARM_PSCI
	default ARM_PSCI_SMC if !HAS_ARM_PSCI_DYNAMIC && (!FORCE_ARM_PSCI_HVC || CPU_VIRT)
	default ARM_PSCI_HVC if !HAS_ARM_PSCI_DYNAMIC && FORCE_ARM_PSCI_HVC && !CPU_VIRT
	default ARM_PSCI_DYN if HAS_ARM_PSCI_DYNAMIC

config ARM_PSCI_SMC
	bool "SMC"
	depends on !HAS_ARM_PSCI_DYNAMIC
	depends on !FORCE_ARM_PSCI_HVC || CPU_VIRT
	help
	  Choose this if the platform uses SMC as a conduit to
	  access PSCI functions.

config ARM_PSCI_HVC
	bool "HVC"
	depends on !HAS_ARM_PSCI_DYNAMIC
	depends on HAS_CPU_VIRT && !CPU_VIRT && !FORCE_ARM_PSCI_SMC
	help
	  Choose this if the platform uses HVC as a conduit to
	  access PSCI functions.

config ARM_PSCI_DYN
	bool "dynamic"
	depends on HAS_ARM_PSCI_DYNAMIC
	help
	  Choose this if the platform supports dynamic configuration
	  at runtime.

endchoice

config ARM_1176_CACHE_ALIAS_FIX
	bool "Use cache restriction to supress aliasing issue on ARM1176"
	depends on ARM_1176
	help
	  The ARM1176 processor might have a memory aliasing problem when
	  using cache sizes of more than 16 KiB cache. Enabling this option
	  enables the workaround of reducing the cache size to 16 KiB.

config ARM_CPU_ERRATA
	bool "Enable CPU errata workarounds"

config EXPLICIT_ASID
	bool "Explicit ASID/VMID allocation"
	depends on ARM_CORTEX_R52 && CPU_VIRT
	help
	  On Cortex-R52 based platforms, the VMID is transmitted on the bus for
	  device memory accesses. This is used by some SOCs as requester
	  authentication in their IO-MPU. Allow a privileged component in the
	  system to explicitly set the VMID to grant access for applications or
	  virtual machines.

config ARM_FAST_INTERRUPTS
	bool "Enable low latency interrupt optimization"
	depends on ARM_V8 && ARM_PROFILE_R && CPU_VIRT && BIT32
	select ARM_CPU_ERRATA if ARM_CORTEX_R52	# Erratum 2918152
	help
	  Armv8-R AArch32 defines a "Fast Interrupts" feature in HSCTLR.FI. It
	  disables some performance features to lower the interrupt latency.
	  Specifically, asynchronous errors and interrupts can interrupt
	  LDM/STM instructions that access Normal memory. Even though the
	  instruction will be restarted after the interrupt was processed,
	  memory and registers referenced by the instruction will have an
	  unknown state.

	  If unsure, say N.

config ARM_ICACHE_FLASH_WAYS
	int "L1 instruction cache ways allocation for Flash interface"
	depends on ARM_CORTEX_R52 && CPU_VIRT
	range 0 4
	default 0
	help
	  On Cortex-R52, the L1 instruction cache supports segregation of cache
	  ways between the Flash and AXIM interfaces. This option allows
	  configuring how many cache ways are allocated to each interface. By
	  default (reset value), all instruction cache ways are assigned to the
	  AXIM interface. Adjusting this setting can optimize performance based
	  on memory access patterns.

config ARM_DCACHE_FLASH_WAYS
	int "L1 data cache ways allocation for Flash interface"
	depends on ARM_CORTEX_R52 && CPU_VIRT
	range 0 4
	default 0
	help
	  On Cortex-R52, the L1 data cache supports segregation of cache ways
	  between the Flash and AXIM interfaces. This option allows configuring
	  how many cache ways are allocated to each interface. By default
	  (reset value), all data cache ways are assigned to the AXIM
	  interface. Adjusting this setting can optimize performance based on
	  memory access patterns.

# SECTION: COMPILING

config THUMB2
	bool "Compile to Thumb-2 object code"
	depends on ARM_V7PLUS && !BIT64
